The present invention relates to a vector divide apparatus, and more specifically to a vector divide apparatus for performing a vector division by repetitively solving a partial quotient with a multiplier.
A vector processor operates at high speed using an arithmetic pipeline, but it is not easy to perform a vector division using a pipeline.
A method of performing a vector division using a pipeline has been proposed as described for example in JP-A-No. 57-17244 or JP-A-No. 60-86671, wherein a large number of multipliers and adders are used. With this method, its hardware becomes very large and the vector processor becomes costly, although the speed of a vector division by the processor can be improved.